1. Field of the Invention
This disclosure relates to a semiconductor device, and more particularly, to a method for forming wire lines such as bit lines and interconnecting contacts such as capacitor contacts by using a multi-layered hard mask.
2. Description of the Related Art
With the improved performance of semiconductor devices (e.g., DRAM devices), design rules have been markedly reduced. The design rule of the semiconductor devices has recently been reduced to about 0.14 μm or less, even to 92 nm or less. Thus, various methods of solving problems caused by a reduction in the design rule during the manufacture of semiconductor devices have been proposed.
Conventionally, wire lines (e.g., word lines or bit lines) of semiconductor devices are typically formed of tungsten silicide (Wsix). However, to improve the speed and performance of devices for reduced design rules, extensive studies have been made of forming word lines (or gates) and/or bit lines by using tungsten (W) having a relatively low resistance.
FIGS. 1 through 4 are schematic cross-sectional diagrams illustrating a conventional method for forming wire lines.
Referring to FIGS. 1 through 4, bit lines are formed using tungsten. Initially, a barrier layer 21 is formed and then a bit line layer 23 is formed. Here, layers such as a first insulating layer 11 and a second insulating layer 15 are formed on a semiconductor substrate (not shown), and then the barrier layer 21 is formed on the second insulating layer 15. An active device such as a transistor may be formed on the semiconductor substrate, and intermediate interconnecting contacts (e.g., direct contacts (DCs)) (not shown) may be formed to penetrate the second insulating layer 15 so as to electrically connect the transistor and bit lines.
To electrically connect the DCs and the transistor, first contact pads (not shown), which penetrate the first insulating layer 11, may be formed to connect the semiconductor substrate and the DCs. As shown in FIG. 1, second contact pads 17 may be formed on the same level with the first contact pads to electrically connect capacitors and the semiconductor substrate (substantially, the transistor). Capacitor contacts (e.g., buried contacts (BCs)) (not shown) penetrate the second insulating layer 15 between bit lines to be electrically connected to the second contact pads 17. In typical capacitor-over-bit line (COB)-type DRAM devices, the capacitor contacts are electrically connected to the second contact pads 17 and penetrate the second insulating layer 15 between the bit lines such that the capacitors are electrically connected to the semiconductor substrate.
Referring to FIG. 1, after the barrier layer 21 and the bit line layer 23 are formed, a silicon nitride (Si3N4) mask layer 30 is formed on the bit line layer 23 to form a hard mask, which will be used as an etch mask during patterning. As shown in FIG. 4, the silicon nitride mask layer 30 is formed to a very thick thickness in order to secure sufficient insulating margins 39 between the bit lines 23 and the BCs (not shown) when a contact hole 18 for the BC is formed. For example, the silicon nitride mask layer 30 may be formed to a thick thickness of about 2000 Å. Meanwhile, the insulating margins may be also referred to as “shoulders.”
Referring back to FIG. 1, after the layers for forming the bit lines 23 are stacked, a photoresist pattern 40 is formed on the silicon nitride mask layer 30.
Referring to FIG. 2, the bit lines 23 are patterned at once by using the photoresist pattern 40 as an etch mask. Alternatively, the silicon nitride mask layer 30 is first patterned by using the photoresist pattern 40 as an etch mask, and then the photoresist pattern 40 is removed. Thereafter, the bit lines 23 are finally formed by using the patterned silicon nitride mask layer, i.e., a hard mask 35, as a mask.
Referring to FIGS. 3 and 4, after the bit lines 23 are formed, silicon nitride spacers 37 are formed to protect the sidewalls of the bit lines 23. To form the silicon nitride spacers 37, a silicon nitride layer of several hundred Åthickness is formed on the sidewalls and then dry etched using an etchback process. Thereafter, a third insulating layer 19 is formed as an interlayer dielectric (ILD), and BC contact holes (18 of FIG. 4) are formed to connect storage nodes of the capacitors (not shown) with an active region of the semiconductor substrate or with the second contact pads 17 connected to the active region. Here, a dry over-etching is carried out to prevent the BC contact holes 18 from being not-open. Thus, as shown in FIG. 4, the shoulders 39 between the BC contact holes 18 and the bit lines 23 may become very narrow.
If the shoulders 39 become narrow, insulation between the capacitor contacts (i.e., the BCs) and the bit lines 23 is unreliable to reduce breakdown voltage value, thus resulting in a single bit failure. Such a problem may likewise occur in gates using tungsten for wire lines.
Also, due to this bitline to BC shoulder issue, the spacers 37 shown in FIG. 3 should be formed, not of silicon oxide, but of silicon nitride having a relatively high dielectric constant. Also, the thickness of the spacers 37 should be held very thick. This leads to an increase in parasitic capacitance, which may adversely affect the sensing efficiency of DRAMs. Accordingly, advanced methods for forming semiconductor devices are required so as to increase shoulder margin and reduce bit line coupling capacitance.
Embodiments of the invention address these and other disadvantages of the conventional art.